The semiconductor industry's continuing demand for memory devices with ever increasing storage densities has led to a corresponding decrease in memory cell size for each new generation of memory device. Scaling of memory cell size, however, can adversely effect the functionality and reliability of these devices. For example, a reduction in EEPROM, EPROM or Flash EEPROM cell size also decreases the surface area shared by the control gate and floating gate. Therefore, the coupling capacitance between the floating gate and the control gate is reduced, and the probability of inaccurately reading the charge stored in the memory cell increases. Analogously, a reduction in DRAM cell size also leads to a reduction in the surface area shared by the two capacitor electrodes. Thus the capacitance of the DRAM cell is reduced, making it more susceptible to "soft" errors. In addition, lower cell capacitance also adversely effects DRAM noise sensitivity, and refresh rate.
In order to offset the resulting reduction of DRAM cell capacitance, and floating gate to control gate coupling capacitance, with shrinking memory cell size, several solutions have been proposed. The use of texturized or roughened semiconductor electrodes for control gates or capacitor plates is one proposed technique for increasing floating gate to control gate coupling capacitance, and DRAM cell capacitance. One technique for forming these textured semiconductor electrodes is to deposit a silicon dioxide layer over a polysilicon film. Low pressure chemical vapor deposition is then used to deposit polysilicon islands onto the silicon dioxide surface. The exposed portion of the silicon dioxide layer is then anisotropically etched to expose a portion of the polysilicon surface. The exposed portion of the polysilicon surface is then anisotropically etched to form depressions within the polysilicon film. The remaining portion of the silicon dioxide layer is then removed and the textured polysilicon layer is then used to fabricate floating gates and capacitor electrodes.
The process for forming the polysilicon islands, however, has a narrow processing window. The nucleation and growth of a polysilicon island is dependent on deposition temperature. Therefore, temperature gradients across a wafer, as well as temperature variations from wafer to wafer, can lead to uniformity and repeatability problems. In addition, polysilicon island formation is also dependent on the morphology and cleanliness of the underlying deposition surface. Thus variations in surface morphology and surface cleanliness can also lead to non-uniform and non-repeatable polysilicon island formation. Consequently, the texture of the resulting polysilicon films can vary within a wafer and from wafer to wafer. Therefore, the electrical characteristics and performance of a given semiconductor device may vary within the same chip or from chip to chip, and may ultimately result in the fabrication of memory devices that are unreliable and non-functional. Accordingly, a need exists for a process that uniformly roughens or texturizes the surface of semiconductor electrodes used in semiconductor devices.